Serial Interface Device Built-In Self Test

ABSTRACT

A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation-in-Part of U.S. application Ser. No.11/162,153, filed Aug. 8, 2005, and included herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a built-in test circuit, moreparticularly a serial interface device built-in test circuit capable ofdetecting command symbols to automatically compensate loopback latency.

2. Description of the Prior Art

In the development of personal computer systems and peripheral devices,bandwidth and speed requirements of the interconnect interface areincreasing. Loads of conventional parallel interfaces areinsufficiently. Therefore, serial interfaces, such as PCI Expressinterface, USB 3.0 interface and SATA interface are widely used intoday's computer system for satisfying such high bandwidth demands. Forexample, the first generation PCI Express provides at least 2.5 Gbps foreach lane; USB 3.0 offers at least 5.0 Gbps for each port; and SATA hasat least 1.5 Gbps capacity for each port. Those serial interfacesutilize higher operational clocks and apply more data lanes/ports toimprove data transmission efficiency, which greatly enhance performanceof computer systems.

Serial interface devices, USB 3.0 devices for instance, coupled to aserial bus, a USB 3.0 bus for instance, usually being operated at ahigh-speed transmission where data volume is large. In order to makesure the accuracy of data transmission, a conventional built-in selftest (BIST) circuit is used to test the serial interface device. A testpattern generator (TPG) and an output response analysis (ORA) arebuilt-in to a port under test. Please refer to FIG. 1. FIG. 1illustrates architecture of conventional built-in self test circuit 100.The built-in self test circuit 100 includes a pattern generator 102, anelastic buffer 104, a pattern register 106, a pattern comparison module108, and a port under test 110. The pattern generator 102 generates atest pattern to the port under test 110 and the pattern register 106,then the elastic buffer 104 receives and transmits the test patterns viathe port under test 110 to the pattern comparison module 108, and thepattern register 106 temporarily stores and transmits the test patternsin a predetermined time to the pattern comparison module 108. The testpattern received by the elastic buffer 104 and the test pattern storedin the pattern register 106 are compared; the pattern comparison module108 determines whether the port under test 110 correctly transmits thetest pattern generated by the pattern generator 102.

The conventional built-in self test circuit 100 does not require anexternal automatically test equipment (ATE) to generate a test vector,also it is not required by the ATE to analyze test results. Thereforethe test bandwidth requirement is less than general test methods, andtest speed is not limited by the ATE speed hence it is more efficient.However, the port under test 110 of serial interface device such as USB3.0 device includes a plurality of loopback paths, which also means thattime required by the test patterns to pass through the port under test110 is not constant, so that the loopback latency cannot be predicted.Therefore the storage capacity of the pattern register 106 must besufficiently large to compensate the loopback latency. Furthermore, thebuilt-in self test circuit 100 will be affected by phase jitter whichcauses errors in the pattern comparison module 108. Moreover, thestorage capacity of the pattern register 106 must be restricted;therefore when the loopback latency becomes too great, the built-in selftest architecture 100 will not operate accurately.

SUMMARY OF THE INVENTION

The claimed invention provides a serial interface device built-in testcircuit for compensating loopback latency.

The claimed invention provides a serial interface device built-in selftest circuit includes: a pattern generator coupled to a port under testfor generating a first test pattern to test a port under test; anelastic buffer coupled to the port under test for receiving a testresult pattern from the port under test, wherein the test result patternis gotten according to the first test pattern; a symbol detector coupledto the elastic buffer for detecting whether a starting symbol is foundin the test result pattern; wherein a second test pattern which issubstantially identical to the first test pattern is generated while thestarting symbol is detected; and a comparison unit for comparing thetest result pattern and the second test pattern.

The claimed invention further provides a self test method for testing aserial interface device, the method includes: utilizing a first testpattern to test a port under test to get a test result pattern accordingto the first test pattern; detecting whether a starting symbol is in thetest result pattern; generating a second test pattern while the startingsymbol is detected, wherein second test pattern is substantiallyidentical to the first test pattern; and comparing the test resultpattern and the second test pattern.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a conventional built-in self test circuit;

FIG. 2 illustrates one embodiment of a serial interface device built-intest circuit of the present invention;

FIG. 3 illustrates a waveform diagram of serial interface devicebuilt-in self test circuit of FIG. 2; and

FIG. 4 illustrates another one embodiment of a serial interface devicebuilt-in test circuit of the present invention.

DETAILED DESCRIPTION

Please refer to FIG. 2. FIG. 2 illustrates one embodiment of serialinterface device built-in test circuit 200 of the invention. Thebuilt-in test circuit 200 is capable of compensating loopback latency ofserial interface devices such as PCI Express devices, USB 3.0 devicesand SATA devices. The built-in test circuit 200 includes a test unit210, a detecting unit 220, and a compare unit 230. The test unit 210includes a first pattern generator 211 and an elastic buffer 212. Thedetecting unit 220 includes a symbol detector 221 and a drive circuit222. The compare unit 230 includes a second pattern generator 232 and alogic unit 231. Furthermore, the built-in self test circuit 200 furtherincludes a test activation circuit 250 and a counter 260. In FIG. 2, aport under test 240 is a port in the serial interface device required tobe tested.

Those skilled in the art should understand sometimes the term “port” andthe term “lane” are alternatively used, and they are essentially thesame. For example, while USB 3.0 devices or SATA devices are indicated,the term “port” is more often used than the term “lane”; however, whilePCI Express devices are specified, the term “lane” is used instead. Themethod of operating the built-in self test circuit 200 will be explainedin the following paragraph.

For a serial data transmission, there is a symbol in each data sequenceto indicate the beginning of the data sequence. For example, thestarting symbol could be a COM symbol. In one embodiment of theinvention, assume a USB 3.0 device is going to be tested. The firstpattern generator 211 generates a first test pattern to test a portunder test 240. Then, a test result pattern is gotten and stored in theelastic buffer 212. The symbol detector 221 detects whether a startingsymbol COM is found in the test result pattern. If there is a startingsymbol in the test result pattern, then the second pattern generator 232generates a second test pattern. In the invention, second test patternis substantially identical to the first test pattern. The logic unit 231compares the test result pattern and the second test pattern todetermine if the port under test 240 carries data accurately. In theembodiment, the test activation circuit 250 is active while a test isperformed; and the first pattern generator is controlled by the testactivation circuit 250. Additional, the drive circuit is used to drivethe second pattern generator to generate the second test pattern.

In the present invention, no matter how many latencies of the port undertest 240 has, the second test pattern is only generated while thestarting symbol COM is detected within the test result pattern. Bycomparing the test result pattern and the second test pattern, the logicunit 231 can determine whether the first test pattern transmitted by theport under test 240 is accurate.

Because there are many loopback paths in the port under test 240,spending time for the test patterns to pass through the port under test240 is uncertain. As a result, it is impossible to estimate the loopbacklatency. However, by detecting the starting symbol COM, it is notnecessary to consider the issue of latency. Furthermore, the counter 260counts clock differences between the second test pattern and the testresult pattern within a predetermined time period. Hence, bit error rate(BER) can be figured out via an error rate detection circuit (not shownin FIG. 2). Besides, the first pattern generator 211 and the secondpattern generator 232 could further couple to a test pattern selector(also not shown in FIG. 2) for selecting various types of test patternsto execute different tests.

Please refer to FIG. 2 and FIG. 3. FIG. 3 illustrates a waveform diagramof built-in self test circuit 200 of FIG. 2. In FIG. 3, Signal CLKrepresents system clock, and each cycle is T. Signal MODELSEL representssignals outputted from the test pattern selector for selecting testpatterns outputted from the first pattern generator 211 and the secondpattern generator 232. Signal EPHYTST represents signals outputted fromthe test activation circuit 250. In one embodiment of the invention,built-in self test circuit 200 would start to test while the signalEPHYTST is asserted, Signal PTNGEN_TXD represents signals outputted fromthe first pattern generator 211; and signal RXEBUF_RXD represents signalreceived by the elastic buffer 212. Signal COMDET represents signalsoutputted from the symbol detector 221. In one embodiment of the presentinvention, the symbol detector 221 asserts the signal COMDET while astarting symbol is detected. Signal PTNCMP_TXD represents signalsgenerated by the second pattern generator 232. Signal PTNCMP_RXD isreceived by the logic unit 231. Signal EPHYERRCNT represents signalsoutputted from the counter 260.

As shown in FIG. 3, while the signal EPHYTST transits from low to highlevel state at 2T, a test is triggered. Then the first pattern generator211 outputs a first test pattern at 3T which leads four COM symbols.More detail, COM_N means the COM symbol in a negative running disparitystatus; and COM_P means the COM symbol in a positive running disparitystatus. At 6T, the signal MODESEL transits from 0 to 1, other symbols,following the four COM symbols, are generated. That is to say, symbolsAAA_N, BBB_P, CCC_N and so forth are sequentially transmitted from 7T.Assume latency of the port under test 240 is four cycles; as a result, atest result pattern is gotten from the port under test 240 at 7T. Thetest result pattern is restored in the elastic buffer 212. As mentionedabove, the signal COMDET is asserted at a high level state from 7T to10T due to the first four COM symbols of the result pattern (i.e. signalRXEBUF_RXD) are detected. Then, the second pattern generator 232accordingly generates a second test pattern at 8T. In one embodiment ofthe invention, the second test pattern is substantially identical to thefirst test pattern. If the port under test 240 is functional well, theresult patter should be the same with the originally inputted patter—thefirst test pattern. However, if the port under test 240 is unable tocorrectly transmit, an error symbols may be found in the result patter.For example, assume the fifth symbol AAA_N of the first test patter isreplaced by an error symbol XXX_X in the result patter, by comparing thesecond test pattern (i.e. signal PTNCMP_TXD) and the result pattern(i.e. signal PTNCMP_RXD), the incorrect transmission is identified.Then, 1 is accumulated by the counter 260 to indicate one differentsymbol is found between signals PTNCMP_TXD and PTNCMP_RXD.

FIG. 4 illustrates another one embodiment of serial interface devicebuilt-in test circuit 300 of the invention. The built-in test circuit300 is capable of compensating loopback latency of serial interfacedevices such as PCI Express devices, USB 3.0 devices and SATA devices.The built-in test circuit 300 includes a pattern generator 310, anelastic buffer 320, a symbol detector 330, and a comparison unit 340.Furthermore, the built-in self test circuit 300 further includes a drivecircuit 350 and a counter 370. In FIG. 3, a port under test 360 is aport in the serial interface device required to be tested. As previouslydiscussed, the port under test 360 could be ports of USB 3.0 devices,ports of SATA devices, lanes of PCI Express devices, or any kind ofports/lanes of serial interface devices.

In this embodiment, assume a USB 3.0 device is going to be tested. Then,please refer to FIG. 4, the driving circuit 350 drives the patterngenerator 310 to generate a first test pattern to test a port under test360. After a few cycles, a test result pattern from the port under test360 is gotten and stored in the elastic buffer 320. Then the symboldetector 330 detects whether there is a starting symbol within the testresult pattern. If there is, the pattern generator 310 generates asecond test pattern. In the present invention, the second test patternis substantially identical to the first test pattern. Then, thecomparison unit 340 compares of the test result pattern and the secondtest pattern to determine if the port under test 360 functions well.

In other words, no matter how many latencies of the port under test 360has, the second test pattern is only generated while the starting symbolis detected from the test result pattern. As a result, it is notnecessary to consider the issue of latency in the present invention.Furthermore, the counter 370 in the present invention counts how manydifferent symbols exist between the second test pattern and the testresult pattern within a predetermined time period. Therefore, bit errorrate (BER) can be estimated.

In conclusion, as the above-mentioned, when a starting symbol isdetected, a second test pattern, identical to the first test pattern, isgenerated. Hence, the present invention can compensate loopback latencyautomatically and a device that stores test patterns of the firstpattern generator is not required, and an error warning is greatlyreduced. Furthermore, the present invention is capable of counting theerror rate, therefore, the port under test can be analyzed moreeffectively.

In comparison to the prior art, the present invention does not considerthe loopback latency and the present invention can reduce the effect ofphase jitter and provides error rate count. Therefore, the presentinvention overcomes the defect of the prior art and hence the accuracyof the test is greatly increased.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention. Accordingly, the abovedisclosure should be construed as limited only by the metes and boundsof the appended claims.

1. A built-in self test circuit comprising: a pattern generator coupledto a port under test for generating a first test pattern to test a portunder test; an elastic buffer coupled to the port under test forreceiving a test result pattern from the port under test, wherein thetest result pattern is gotten according to the first test pattern; asymbol detector coupled to the elastic buffer for detecting whether astarting symbol is found in the test result pattern; wherein a secondtest pattern which is substantially identical to the first test patternis generated while the starting symbol is detected; and a comparisonunit for comparing the test result pattern and the second test pattern.2. The built-in self test circuit of claim 1 further comprising acounter coupled to the comparison unit for accumulating how manydifferent symbols exist between the test result pattern and the secondtest pattern.
 3. The built-in self test circuit of claim 2 wherein thecounter is further coupled to an error rate detecting circuit forfiguring out an error rate of the port under test.
 4. The built-in selftest circuit of claim 1 wherein the second test pattern is generated bythe pattern generator.
 5. The built-in self test circuit of claim 1 thebuilt-in self test circuit further comprises a second pattern generatorfor generating the second test pattern.
 6. The built-in self testcircuit of claim 1 further comprising a drive circuit for driving thepattern generator.
 7. The built-in self test circuit of claim 1 whereinthe built-in self test circuit further comprises a counter coupled tothe comparison unit for estimating a bit error rate of the port undertest.
 8. The built-in self test circuit of claim 1 wherein the built-inself test circuit is applies to a serial interface device.
 9. Thebuilt-in self test circuit of claim 1 wherein the built-in self testcircuit is applies to a USB 3.0 device.
 10. The built-in self testcircuit of claim 1 wherein the built-in self test circuit is applies toa SATA device.
 11. A self test method for testing, the methodcomprising: utilizing a first test pattern to test a port under test toget a test result pattern according to the first test pattern; detectingwhether a starting symbol is in the test result pattern; generating asecond test pattern while the starting symbol is detected, whereinsecond test pattern is substantially identical to the first testpattern; and comparing the test result pattern and the second testpattern.
 12. The method of claim 11 further comprising counting how manydifferent symbols exist between the test result pattern and the secondtest pattern, and estimating an error rate of the port under test. 13.The method of claim 11 wherein the self test is applied to the portunder test of a serial interface device.
 14. The method of claim 11wherein the self test is applied to the port under test of a USB 3.0device.
 15. The method of claim 11 wherein the self test is applied tothe port under test of a SATA device.